WaferSense by CyberOptics SemiconductorWaferSense by CyberOptics Semiconductor
December 2009
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Reports from the Fab

Fab Establishes Co-Planarity Across Vertical Diffusion Process to Reduce Wafer Particle Contamination, Improve Yield


The User: A 300 mm fab for one of the world’s largest chipmakers.

Multi-Wafer Diffusion Process Calls for Co-Planarity Among Stations

Wafers being processed at a 300 mm fab’s vertical diffusion furnace received micro scratches during uneven handling and z-axis movement that led to particle contamination, scrap and shattered wafers. The lack of co-planarity among the tools and wafers throughout the multi-wafer process reduced yield and led to prolonged equipment and staff downtime to troubleshoot contamination sources.

Wafers in the process traveled, 25 at a time, in a front open unified pod (FOUP) to the robot end effector, which fed five full FOUPs, or 125 wafers, into the wafer boat that transferred them up into the furnace, operating at approximately 1,200° C.

The number of wafers being handled and narrow pitch between wafers in FOUPs and the wafer boat made wafers traveling through the process susceptible to damaging micro scratches if a station in the process wasn’t level...
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Technically Speaking

Gap Measurement With Repeat Test


by Hayashi Yukinobu, Applications Engineer, CyberOptics Semiconductor (as reported to Hayashi by fab managers)


Pedestal leveling of a single wafer PECVD chamber uses Double Nuts for locking screws during adjustments. The data below shows the change of distance between the showerhead to pedestal and its Tilt, per diameter of the wafer, by rotating the Susceptor Locking Nut with WaferSense AGS...
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